A field-programmable gate array (FPGA) based system for digital filtering in a neonatal heart rate monitoring system is presented. The system employs electric potential sensors (EPS) and contains a single hardware filter stage for antialiasing. The remaining digital signal processing required to provide a clinical standard electrocardiogram (ECG) is performed on the FPGA (myRIO 1900, National Instruments Corporation of Austin, Austin, TX, USA). This is compared with a previous microprocessor version (Raspberry Pi 3, BCM2837 processor, Raspberry Pi Ltd, Cambridge, UK) containing a dual hardware/software filtering scheme, with the aim of simplifying the analog front end and allowing for reconfigurable filtering in the digital domain. A custom neonate phantom was employed to emulate real world conditions and ambient noise. The developed FPGA system was shown to have a signal quality comparable with the microprocessor implementation, with an average signal-to-noise ratio loss of 2%. A 12 dB increase in the attenuation of the predominant 50 Hz noise was shown, indicating filter effectiveness gains. The phantom was used to broadcast data from the preterm infant cardio-respiratory signals database (PICSDB) and the FPGA filtering scheme was shown to remove the majority of the ambient 50 Hz noise with an average reduction of 30 dB, and provided a clean ECG signal. These results demonstrate that FPGA-filtered EPS ECGs have comparable signal quality to the combined HW/SW filtering implementation, with a reduction in complexity and power consumption.
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